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ST
Sitronix
: - 2.7 to 5.5V 8-4-MPU 64 x 16- RAM (DDRAM 16 x 4 , LCD16 X 2) 64 x 256- RAMGDRAM 2M- ROM (CGROM) 8192 (16x16 ) 16K- ROM (HCGROM) 126 (16x8 ) 64 x 16- RAM (CGRAM) 15 x 16- 240 ICON RAMIRAM 33-common x 64-segment (2 ) RESET (XRESET) Segment 16x2
ST7920
LCD /
Normal mode (450uA Typ VDD=5V) Standby mode (30uA Max VDD=5V) Sleep mode (3uA Max VDD=5V) VLCD (V0~ Vss): 7V - Display clear - Return home - / Display on/off - / Cursor on/off - Display character blink - Cursor shift - Display shift - Vertical line scroll - By_line reverse display - Sleep mode Booster (2 ) 1/33 Duty
ST7920 LCD/IC 8, 4RAM LCD/IC ST7920 ROM 819216X1612616X8 64x256GDRAM240ICON RAMST7920CGRAM 416X16 ST7920 (2.7V to 5.5V) ST7920 LCD33common64segmentSegmentST7921 Segment ST79201824ST7921216 ST7920-0A ST7920-0B BIG-5 GB
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ST7920
ST7920 Specification Revision History
1. VCC VDD 2. VLCD VCC-V5 V0-VSS C1.7 2000/12/15 3. DC characteristics input High voltage(Vih) 0.7VDD 4. DC characteristics output High voltage(Voh) 0.8VDD 1. Chip Size 2. ICON 256 240 3. XOFF normal high sleep Low normal low sleep High C1.8 2001/03/01 4. XOFF 5. ST7920 4,5,6 PIN (4,5,6 test pin) 6. CAP1P,CAP1M,CAP2M 1. 2. C1.9 2001/05/28 3. 4. 5. Icon RAM TABLE (TABLE-6) Booster (PAGE-29) AC Characteristics 2Line 16 Chinese Word(32Com X 256Seg)
1. Register initial C2.0 2001/07/03 2. CAP1M CAP1P (PAGE-30)
1. Page 41 booster circuit (PSB,OSC1) C2.0b 2001/08/14 2. Page 18 SL flag
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ST7920
RESI Reset Circuit CLK PSB
RESO
CL1 CL2 M Timing Generator DOUT
RS RW E
Instruction Register (IR) MPU Interface Instruction Decoder Display Data RAM (DDRAM) 60 x 16 bits 33/49bit shift register
COM1 to Common COM33 Signal Driver
SEG1 to SEG64 64-bit shift register 64-bit latch circuit Segment Signal Driver
DB4 to DB7 Input/ Output Buffer Data Register (DR) Busy Flag
Address Counter
DB0 to DB3
LCD Drive Voltage Selector
Graphic RAM (GRAM) 1024 x 16 bits
Half size Character ROM (HCGROM) 1024x16 bits
Character Generator RAM (CGRAM) 1024 bits
Character Generator ROM (CGROM) 2M bits
Cursor Blink Scroll Controller
Vss
Parallel/Serial converter and Attribute Circuit
VDD XOFF XRESET V0 V1 V2 V3 V4
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Pad
30 1
ST7920
31
136
"ST7920" PAD
(0,0)
99 68
1
69 98
: : 5305 X 4074 Pad : 125
: Pad Pad : 90 X 90 : m
* chip substrate VSS
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 V0 V1 V2 N.C. N.C. N.C. V3 V4 VSS VDD CL1 CL2 VDD M DOUT RS RW E VSS OSC1 OSC2 PSB D0 D1 D2 D3 D4 D5 D6 D7 XOFF VOUT CAP3M CAP1P CAP1M CAP2P CAP2M X -2548 -2548 -2548 -2548 -2548 -2548 -2548 -2548 -2548 -2548 -2548 -2548 -2548 -2548 -2548 -2548 -2548 -2548 -2548 -2548 -2548 -2548 -2548 -2548 -2548 -2548 -2548 -2548 -2548 -2306 -2181 -2056 -1931 -1806 -1681 -1556 -1431 Y 1812 1688 1562 1438 1312 1188 1062 938 812 688 562 438 312 188 62 -62 -188 -312 -438 -562 -688 -812 -938 -1062 -1188 -1312 -1438 -1562 -1688 -1812 -1933 -1933 -1933 -1933 -1933 -1933 -1933 -1933 : um 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 VD2 C[1] C[2] C[3] C[4] C[5] C[6] C[7] C[8] C[9] C[10] C[11] C[12] C[13] C[14] C[15] C[16] C[17] C[18] C[19] C[20] C[21] C[22] C[23] C[24] C[25] C[26] C[27] C[28] C[29] C[30] C[31] C[32] C[33] S[64] S[63] S[62] S[61] X -1306 -1181 -1056 -931 -806 -681 -556 -431 -306 -181 -56 69 194 319 444 569 694 819 944 1069 1194 1319 1444 1569 1694 1819 1944 2069 2194 2319 2548 2548 2548 2548 2548 2548 2548 2548 Y -1933 -1933 -1933 -1933 -1933 -1933 -1933 -1933 -1933 -1933 -1933 -1933 -1933 -1933 -1933 -1933 -1933 -1933 -1933 -1933 -1933 -1933 -1933 -1933 -1933 -1933 -1933 -1933 -1933 -1933 -1812 -1688 -1562 -1438 -1312 -1188 -1062 -938
XRESET -2548
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77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115
S[60] S[59] S[58] S[57] S[56] S[55] S[54] S[53] S[52] S[51] S[50] S[49] S[48] S[47] S[46] S[45] S[44] S[43] S[42] S[41] S[40] S[39] S[38] S[37] S[36] S[35] S[34] S[33] S[32] S[31] S[30] S[29] S[28] S[27] S[26] S[25] S[24] S[23] S[22]
X 2548 2548 2548 2548 2548 2548 2548 2548 2548 2548 2548 2548 2548 2548 2548 2548 2548 2548 2548 2548 2548 2548 2319 2194 2069 1944 1819 1694 1569 1444 1319 1194 1069 944 819 694 569 444 319
Y -812 -688 -562 -438 -312 -188 -62 62 188 312 438 562 688 812 938 1062 1188 1312 1438 1562 1688 1812 1933 1933 1933 1933 1933 1933 1933 1933 1933 1933 1933 1933 1933 1933 1933 1933 1933
116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136
S[21] S[20] S[19] S[18] S[17] S[16] S[15] S[14] S[13] S[12] S[11] S[10] S[9] S[8] S[7] S[6] S[5] S[4] S[3] S[2] S[1]
X 194 69 -56 -181 -306 -431 -556 -681 -806 -931 -1056 -1181 -1306 -1431 -1556 -1681 -1806 -1931 -2056 -2181 -2306
Y 1933 1933 1933 1933 1933 1933 1933 1933 1933 1933 1933 1933 1933 1933 1933 1933 1933 1933 1933 1933 1933
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PAD
XRESET PSB
11 23

LOW : 0: 1: 8/4- 0: () Busy 1: () 1: 0: 0: 1: / 4- ST7920 DB7 busy 4- ST7920 4 Segment DOUT DOUT Segment LCD AC Segment Common Segment LCD V0 - V4 7 V VDD : 2.7V 5.5V VSS: 0V OSC1 (540KHz) 5.0V R=33K 2.7V R=18K LCD
RS(CS*)
17
RW(SID*)
18
E(SCLK*)
19
D4 to D7
2831
/
D0 to D3
2427
/
CL1 CL2 M DOUT COM1 to COM33 SEG1 to SEG64 V0 to V4 VDD Vss
12 13 15 16 4072 13673 13 7,8 10,14 9,20

Segment Segment Segment Segment LCD LCD
OSC1, OSC2
21,22
/
VOUT 33 Note: The OSC pin must have the shortest wiring pattern of all other pins.To prevent noise from other signal lines , it should also be enclosed with the largest GND pattern possible. Poor noise characteristics on the OSC line will result in malfunction , or adversely affect the clock's duty ratio.
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PAD
CAP3M CAP1P CAP1M CAP2M XOFF CAP2P VD2 N.C. N.C. N.C.
34 35 36 38 32 37 39 4 5 6
/

LCD() NORMAL=LOW SLEEP MODE =HIGH ( 3.5V)
Note: 1. VDD>=V0>=V1>=V2>=V3>=V4 must be maintained 2. Two clock options: 3. VOUT LCD R1...R5 20K(ohm) VOUT
R=33K (VDD=5.0V) R=18K (VDD=2.7V)
OSC1 R
OSC2 Clock
OSC1
OSC2
(VDD=5V) 800 700 (uA) 600 500 400 300 200 100 0 (KHz)
(VDD=5V) 900 800 700 600 500 400 300 200 100 0
10 0
(K)
(K)
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5
5
25
40
60
25
40
60
80
15
80
15
ST7920
LCD XOFF
XOFF NORMAL=LOW , SLEEP MODE =HIGH
XOFF (1) VLCD=VOUT VLCD=VDD
51K
VLCD=Vout
XOFF
PNP (8550 or 3906) V0
V1
V2
V3
V4
VLCD=+5V
XOFF (2) VLCD>VDD
XOFF CMOS (4049) VLCD 51K
PNP (8550 or 3906) V0
V1
V2
V3
V4
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ST7920
ST79208-,4-PSB PSB"1"8/4-"0" ST79208-DR IRDRDDRAM/CGRAM/GDRAMIRAMRAM DRRAM RSRW4 RS L L H H RW L H L H MPUIR BFAC MPUDR MPUDR
BF BF"1" BFBF"0"ST7920 ST7920 BF AC ACDDRAM/CGRAM/IRAM/GDRAMIR DDRAM/CGRAM/IRAM/GDRAMACRS"0" RW"1"ACDB6DB0 ROMHCGROM ROM (CGROM) ST7920 ROM 8192 16 x 16 126 16 x 8 DDRAM DDRAM CGROM
RAM (CGRAM) ST7920 RAM 16x16 CGRAM CGRAM DDRAM
ICON RAMIRAM ST7920 240 ICON 15 IRAM IRAM 16 IRAM IRAM D15D8 D7D0
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RAMDDRAM RAM 64x2 4 16 64 RAM CGROMHCGROM CGRAM ST7920 HCGROM CGRAM CGROM DDRAM 0000H0006H CGRAM 02H7FH A1 BIG5A140D75F GB(A1A0F7FF) 1. 2. 3. 8 DDRAM 02H7FH CGRAM 16 DDRAM 0000H0002H0004H 16 DDRAM A140HD75FH (BIG5) , A1A0HF7FFH (GB) 16 DDRAM D15D8 D7D0 Table 5 CGRAM DDRAM 0006H
CGRAM Address conuter ( Table 4)
80 Si
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
HLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHL t ronix ST7920 .. ... Table 4 ( )
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RAMGDRAM RAM 64x32 ( RAM ) 256x64 RAM GDRAM ( ) 8 RAMAC, RAM 1. Y RAM 2. X RAM 3. D15D8 RAM ( Bytes) 4. D7D0 RAM ( Bytes) Table-8
LCD LCD 33 common 64 segment LCD segment CGRAM/CGROM 64 segment 33 common common segment 64 segment
/ ST7920 (address counter) DDRAM
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DDRAM CGRAM CGRAM CGRAM ) ) ) ( ( ( B B B B B B B BB B DDDDDDDDDDDDDDDD B15~ B4 3 2 1 0 5 4 3 2 1 0 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 543210 00000000010001100000 00011111111001000000 00100001000001000100 00110001000001111110 01000010010010000100 01010011110010000100 01100110010101001000 01111010011001001000 0 X 00 X 00 10000010010001010000 10010010010000010000 10100010010000100000 10110011110000100000 11000010010001000000 11010000000010000000 11100000000100000000 11110000000000000000 00000000110000000110 00010001101000000100 00100010000100110100 00110101110110100100 01001000000010100100 01010111111100100100 01100100000100100100 01110111111100100100 0 X 01 X 01 10000100000100100100 10010111111100100100 10100100000000100100 10110111111110 00100 11001010000010100100 11011011111110011100 11101010000010001000 11110000000000000000
Table 5 DDRAM CGRAM CGRAM
1. DDRAM () 1 2 CGRAM 4 5 (2 :4 ). 2. CGRAM 0 3 16 4 16 16 OR . 3. CGRAM 0 15 ( 15 ). 4. CGRAM DDRAM 4 15 0 0 3
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ICON RAM
SR "0", IRAM AC3....AC0
ICON RAM D8
SEG7 SEG23 SEG39 SEG55 SEG71 SEG87
D7
SEG8 SEG24 SEG40 SEG56 SEG72 SEG88
AC3 AC2 AC1 AC0 D15 D14 D13 D12 D11 D10 D9
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SEG0 SEG16 SEG32 SEG48 SEG64 SEG80 SEG96 SEG1 SEG17 SEG33 SEG49 SEG65 SEG81 SEG97 SEG2 SEG18 SEG34 SEG50 SEG66 SEG82 SEG98 SEG3 SEG19 SEG35 SEG51 SEG67 SEG83 SEG4 SEG20 SEG36 SEG52 SEG68 SEG84 SEG5 SEG21 SEG37 SEG53 SEG69 SEG85 SEG6 SEG22 SEG38 SEG54 SEG70 SEG86
D6
SEG9 SEG25 SEG41 SEG57 SEG73 SEG89
D5
SEG10 SEG26 SEG42 SEG58 SEG74 SEG90
D4
SEG11 SEG27 SEG43 SEG59 SEG75 SEG91
D3
SEG12 SEG28 SEG44 SEG60 SEG76 SEG92
D2
SEG13 SEG29 SEG45 SEG61 SEG77 SEG93
D1
SEG14 SEG30 SEG46 SEG62 SEG78 SEG94
D0
SEG15 SEG31 SEG47 SEG63 SEG79 SEG95
SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111
SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 SEG132 SEG133 SEG134 SEG135 SEG136 SEG137 SEG138 SEG139 SEG140 SEG141 SEG142 SEG143 SEG144 SEG145 SEG146 SEG147 SEG148 SEG149 SEG150 SEG151 SEG152 SEG153 SEG154 SEG155 SEG156 SEG157 SEG158 SEG159 SEG160 SEG161 SEG162 SEG163 SEG164 SEG165 SEG166 SEG167 SEG168 SEG169 SEG170 SEG171 SEG172 SEG173 SEG174 SEG175 SEG176 SEG177 SEG178 SEG179 SEG180 SEG181 SEG182 SEG183 SEG184 SEG185 SEG186 SEG187 SEG188 SEG189 SEG190 SEG191 SEG192 SEG193 SEG194 SEG195 SEG196 SEG197 SEG198 SEG199 SEG200 SEG201 SEG202 SEG203 SEG204 SEG205 SEG206 SEG207 SEG208 SEG209 SEG210 SEG211 SEG212 SEG213 SEG214 SEG215 SEG216 SEG217 SEG218 SEG219 SEG220 SEG221 SEG222 SEG223 SEG224 SEG225 SEG226 SEG227 SEG228 SEG229 SEG230 SEG231 SEG232 SEG233 SEG234 SEG235 SEG236 SEG237 SEG238 SEG239 ---------------------------------
Table 6
ICON RAM Segment
Table 7
16x8
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0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
GDRAMX ........... 1
15
GGGG DDDD RRRR AAAA MMMM YYYY

...........
...........
b15 b14 b13
...........
b0
Table 8
GDRAM
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ST7920
) 1: (RE=0:

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DDRAM "20H" DDRAM 0 0 0 0 0 0 0 0 0 1 AC"00H" DDRAM AC"00H" 0 0 0 0 0 0 0 0 1 X DDRAM 0 0 0 0 0 0 0 1 I/D S D=1: ON 0 0 0 0 0 0 1 D C B C=1: ON B=1: ON 0 0 0 0 0 1 S/C R/L X X DDRAM DL=1 8-BIT 0 0 0 0 1 DL X 0 RE DL=0 4-BIT X X RE=1: RE=0: CGRAM DDRAM BF 1 RAM RAM 1 1 D7 D6 D5 D4 D3 D2 D1 D0 (DDRAM/CGRAM/IRAM/GDRAM) 0 D7 D6 D5 D4 D3 D2 D1 D0 (DDRAM/CGRAM/IRAM/GDRAM) RAM 72 us 0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 0 0 1 0 AC6 AC5 AC4 AC3 AC2 AC1 AC0 0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 CGRAM AC ) SR=0 ( RAM 72 us 72 us 72 us 72 us 72us 72us 1.6 ms
(540KHZ)
/
DDRAM AC AC6 0 72 us
BF AC RAM 72 us 0 us
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) 2: (RE=1:

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RAM 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 (Com1..32 , Com33 ICON ) SR=1: ) SR SR=0: IRAM ( SR=0: CGRAM ( ) 4 0 0 0 0 0 0 0 1 R1 R0 R1,R0 00 SL=1: 0 0 0 0 0 0 1 SL X X SL=0: DL=1 8-BIT DL=0 4-BIT 0 0 0 0 1 DL X 1 RE RE=1: G 0 RE=0: G=1 : ON G=0 : OFF IRAM 0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 SR=1: AC5~AC0 SR=0: AC3~AC0 ICON RAM GDRAM AC RAM 0 0 1 ( 0 0 0 AC3 AC2 AC1 AC0 ) AC6...AC0 AC3...AC0 AC6 AC5 AC4 AC3 AC2 AC1 AC0 72 us 72 us 72 us 72 us 72 us 72 us 72 us
(540KHZ)
1. ST7920 ST7920 BF BF 0 BF 2. "RE""RE" "RE""RE"
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(Register flag) (RE=0: )
0 0 0 0
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 I/D S
,DDRAM AC 1
1
/ 0 0 0 0 0 0 1 D C
0
B
,, ALL OFF 0
0 0 0 0 0 1 S/C R/L
0
X
0
X

X
0 0 0 0 1 DL X
X
0 RE X X
8 BIT MPU ,
1
0
(Register flag) (RE=1: )
RAM 0 0 0 0 0 0 0 1 R1 0 0 0 0
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 SR
IRAM or CGRAM 0
R0
0
0 0 0 0 0 0 1 SL X
0
X
1
1 RE

0
0
0
0
1
DL
X
G
0
OFF 0
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RS
RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Code
0
0
0
0
0
0
0
0
1
DDRAM "20H"(space code) DDRAM AC "00H", I/D "1" AC 1
RS
RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Code
0
0
0
0
0
0
0
1
x
DDRAM AC"00H" DDRAM
RS
RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Code
0
0
0
0
0
0
1
I/D
S
I/D : I/D = "1", ,DDRAM AC 1 I/D = "0", ,DDRAM AC 1 S:
S H H
I/D H L
DESCRIPTION
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RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Code
0
0
0
0
0
1
D
C
B
,, ON/OFF D : ON/OFF D = "1", ON D = "0", OFF , DDRAM C : ON/OFF C = "1", ON. C = "0", OFF. B : ON/OFF B = "1", ON,. B = "0", . OFF
RS
RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Code
0
0
0
0
1
S/C R/L
x
x
DDRAM S/C L L H H R/L L H L H
Description
(display), (display),
AC Value AC=AC-1 AC=AC+1 AC=AC AC=AC
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RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Code
0
0
0
1
DL
X
RE
x
x
DL : 4/8 BIT DL = "1", 8 BIT MPU DL = "0", 4 BIT MPU RE : RE = "1", RE = "0", RE DL DL RE FLAG CGRAM
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0 Code
0
0
1
AC5 AC4 AC3 AC2 AC1 AC0
CGRAM AC AC 00H..3FH ) SR=0 ( RAM DDRAM
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Code
0
1
AC6 AC5 AC4 AC3 AC2 AC1 AC0
DDRAM AC. AC 80H..8FH AC 90H..9FH AC A0H..AFH AC B0H..BFH BF
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Code
1
BF
AC6 AC5 AC4 AC3 AC2 AC1 AC0
BFAC
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BF = "1", BF = "0".
RAM
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 Code
0
D7
D6
D5
D4
D3
D2
D1
D0
RAM (AC) RAM (CGRAM,DDRAM,IRAM.....)(2-Bytes) BYTE AC
RAM
RS
RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 Code
1
D7
D6
D5
D4
D3
D2
D1
D0
RAM , (AC) (CGRAM,DDRAM,IRAM.....) DUMMY READ DUMMY READ DUMMY READ
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RS
RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Code
0
0
0
0
0
0
0
0
1
RAM RAM
RS
RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Code
0
0
0
0
0
0
0
1
SR
SR = "1", ) ) CGRAM ( SR = "0", IRAM (
RS
RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Code
0
0
0
0
0
0
1
R1
R0
4 R1,R0 00 R1 L L H H R0 L H L H
Description

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Code
0
0
0
0
0
1
SL
0
0
SL=1: SL=0:
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RS
RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Code
0
0
0
1
DL
x
RE
G
x
DL : 4/8 BIT DL = "1", 8 BIT MPU DL = "0", 4 BIT MPU RE : RE = "1", RE = "0", G : G = "1", ON G = "0", OFF RE DL, G DL G RE FLAG IRAM
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0 Code
0
0
1
AC5 AC4 AC3 AC2 AC1 AC0
SR=1: AC5~AC0 SR=0: AC3~AC0 ICON RAM RAM
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Code
0
1
AC6 AC5 AC4 AC3 AC2 AC1 AC0
GDRAM AC () AC6...AC0 AC3...AC0 RAM AC(X ),=0FH 00H
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PSBST7920 DL FLAG 8-4- ( RS , RW , E , DB0..DB7 ) (CGRAM,DDRAM,IRAM.....) DUMMY READ DUMMY READ DUMMY READ 4-4DB7~DB4 DB7~DB44DB3~DB0DB7~DB4 4-DB3~DB0
RS R/W
E
DB0-DB7
Instruction Dummy
RAM
Timing Diagram of 8-bit Parallel Bus Mode Data Transfer
RS R/W
E Upper Low DB0-DB7
4-bit 4-bit
Upper Low
4-bit 4-bit
Upper Low
4-bit 4-bit
Instruction
Dummy
RAM
Timing Diagram of 4-bit Parallel Bus Mode Data Transfer
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PSBST7920 SCLKSID
ST7920CSCS SCLKCSST7920 ST7920 SCLKSIDCS
ST7920SCLK ST7920/
1 RW RS0
RWRS4 DB7~DB4LSB4DB3~DB0 LSB0
CS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCLK SID
1 1 1 1 1 RW RS 0 D7 D6 D5 D4 0 0 0 0 D3 D2 D1 D0 0 0 0 0
Synchronizing Bit string
Higher data 1st byte
Lower data 2nd byte
Timing Diagram of Serial Mode Data Transfer
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ST7920
8051
;-------------------------------------------------------------; Write data from A into INSTRUCTION Register ;-------------------------------------------------------------WRINS: SETB CS SETB SID ; SID = 1 CLR SCLK SETB SCLK ; READ DATA FROM SID CLR SCLK SETB SCLK ; READ DATA FROM SID CLR SCLK SETB SCLK ; READ DATA FROM SID CLR SCLK SETB SCLK ; READ DATA FROM SID CLR SCLK SETB SCLK ; READ DATA FROM SID CLR SCLK CLR SID ; SID = 0 SETB SCLK ; READ DATA FROM SID CLR SCLK SETB SCLK ; READ DATA FROM SID CLR SCLK SETB SCLK ; READ DATA FROM SID CLR SCLK MOVBIT SID, A.7 ; SID = A.7 SETB SCLK ; READ DATA FROM SID CLR SCLK MOVBIT SID, A.6 ; SID = A.6 SETB SCLK ; READ DATA FROM SID CLR SCLK MOVBIT SID, A.5 ; SID = A.5 SETB SCLK ; READ DATA FROM SID CLR SCLK MOVBIT SID, A.4 ; SID = A.4 SETB SCLK ; READ DATA FROM SID CLR SCLK CLR SID ; SID = 0 SETB SCLK ; READ DATA FROM SID CLR SCLK SETB SCLK ; READ DATA FROM SID CLR SCLK SETB SCLK ; READ DATA FROM SID CLR SCLK SETB SCLK ; READ DATA FROM SID CLR SCLK MOVBIT SID, A.3 ; SID = A.3 SETB SCLK ; READ DATA FROM SID CLR SCLK MOVBIT SID, A.2 ; SID = A.2 SETB SCLK ; READ DATA FROM SID CLR SCLK MOVBIT SID, A.1 ; SID = A.1 SETB SCLK ; READ DATA FROM SID CLR SCLK MOVBIT SID, A.0 ; SID = A.0 SETB SCLK ; READ DATA FROM SID CLR SCLK CLR SID ; SID = 0 SETB SCLK ; READ DATA FROM SID CLR SCLK SETB SCLK ; READ DATA FROM SID CLR SCLK SETB SCLK ; READ DATA FROM SID CLR SCLK SETB SCLK ; READ DATA FROM SID CLR SCLK CLR CS CALL DLY8 RET
;------------------------------------------------; Write data from A into DATA Register ;------------------------------------------------WRDATA: SETB CS SETB SID ; SID = 1 CLR SCLK SETB SCLK ; READ DATA FROM SID CLR SCLK SETB SCLK ; READ DATA FROM SID CLR SCLK SETB SCLK ; READ DATA FROM SID CLR SCLK SETB SCLK ; READ DATA FROM SID CLR SCLK SETB SCLK ; READ DATA FROM SID CLR SCLK CLR SID ; SID = 0 SETB SCLK ; READ DATA FROM SID CLR SCLK SETB SID ; SID = 1 SETB SCLK ; READ DATA FROM SID CLR SCLK CLR SID ; SID = 0 SETB SCLK ; READ DATA FROM SID CLR SCLK MOVBIT SID, A.7 ; SID = A.7 SETB SCLK ; READ DATA FROM SID CLR SCLK MOVBIT SID, A.6 ; SID = A.6 SETB SCLK ; READ DATA FROM SID CLR SCLK MOVBIT SID, A.5 ; SID = A.5 SETB SCLK ; READ DATA FROM SID CLR SCLK MOVBIT SID, A.4 ; SID = A.4 SETB SCLK ; READ DATA FROM SID CLR SCLK CLR SID ; SID = 0 SETB SCLK ; READ DATA FROM SID CLR SCLK SETB SCLK ; READ DATA FROM SID CLR SCLK SETB SCLK ; READ DATA FROM SID CLR SCLK SETB SCLK ; READ DATA FROM SID CLR SCLK MOVBIT SID, A.3 ; SID = A.3 SETB SCLK ; READ DATA FROM SID CLR SCLK MOVBIT SID, A.2 ; SID = A.2 SETB SCLK ; READ DATA FROM SID CLR SCLK MOVBIT SID, A.1 ; SID = A.1 SETB SCLK ; READ DATA FROM SID CLR SCLK MOVBIT SID, A.0 ; SID = A.0 SETB SCLK ; READ DATA FROM SID CLR SCLK CLR SID ; SID = 0 SETB SCLK ; READ DATA FROM SID CLR SCLK SETB SCLK ; READ DATA FROM SID CLR SCLK SETB SCLK ; READ DATA FROM SID CLR SCLK SETB SCLK ; READ DATA FROM SID CLR SCLK CLR CS CALL DLY8 RET
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ST7920
8- POWER ON Wait time >40ms
XRESET LOW HIGH
Function set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 X 0 X X
Wait time >100uS
Function set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 X 0 X X
Wait time >37uS
Display ON/OFF control
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 D C B
Wait time >100uS
Display clear
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 1
Wait time >10mS
Entry mode set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 I/D S
Initialization end
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ST7920
4- POWER ON Wait time >40ms
XRESET LOW HIGH
Function set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 X X X X
Wait time >100uS
Function set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 X 0 0 1 X 0 X X X X X X X X X
Wait time >100uS
Display ON/OFF control
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 0 D 0 C 0 B X X X X X X X X
Wait time >100uS
Display clear
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 0 1 X X X X X X X X
Wait time >10mS
Entry mode set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 0 I/D 0 S X X X X X X X X
Initialization end
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ST7920
Booster
Vout
5.4V
Vss + + Cap1M
VDD
VD2 Cap1P
VD2
2.7V Vout x Cap2M Cap2P Cap3M Vout
Vss
VDD Tres XRESET
Trw
XRESET pulse width RESET start time
Trw Tres
10us 50ns
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ST7920
LCD (1/33 duty , 1/5 bias )
540KHZ 1 clock cycle time = 1.85us 1 frame = 1.85us x 300 x 33 = 18315us=18.3ms
300 clocks 1 2 3 4 33 1 2 3 4 33 1 2 3 4 33
V0 V1 V2 COM1 V3 V4 VSS
V0 V1 V2 COM2 V3 V4 VSS
V0 V1 V2 COM33 V3 V4 VSS
SEGx off
V0 V1 V2 V3 V4 VSS
SEGx on
V0 V1 V2 V3 V4 VSS
1 frame
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ST7920
Absolute Maximum Ratings
Characteristics Power Supply Voltage LCD Driver Voltage Input Voltage Operating Temperature Storage Temperature Symbol VDD VLCD VIN TA TSTO Value -0.3V to +5.5V -0.3V to +7.0V -0.3V to VDD+0.3V -20oC to + 85oC -55oC to + 125oC
DC Characteristics ( TA = 25oC , VDD = 2.7 V - 4.5 V )
Symbol VDD VLCD ICC Characteristics Operating Voltage LCD Voltage
Test Condition
V0-VSS
Min. 2.7 3.0 -
Typ. 0.20
Max. 5.5 7 0.45
Unit V V mA
Power Supply Current fOSC = 530KHz, VDD=3.0V Rf=18K
VIH1
Input High Voltage (Except OSC1)
-
0.7VDD
-
VDD
V
VIL1
Input Low Voltage (Except OSC1)
-
- 0.3
-
0.6
V
VIH2
Input High Voltage (OSC1)
-
VDD - 1
-
VDD
V
VIL2
Input Low Voltage (OSC1)
-
-
-
1.0
V
VOH1
Output High Voltage (DB0 - DB7)
IOH = -0.1mA
0.8VDD
-
VDD
V
VOL1
Output Low Voltage (DB0 - DB7)
IOL = 0.1mA
-
-
0.1
V
VOH2
Output High Voltage (Except DB0 - DB7)
IOH = -0.04mA
0.8VDD
-
VDD
V
VOL2
Output Low Voltage (Except DB0 - DB7)
IOL = 0.04mA
-
-
0.1VDD
V A A
ILEAK IPUP
Input Leakage Current Pull Up MOS Current
VIN = 0V to VDD VDD = 3V
-1 22
27
1 32
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ST7920
DC Characteristics ( TA = 25oC, VDD = 4.5 V - 5.5 V )
Symbol VDD VLCD ICC Characteristics Operating Voltage LCD Voltage Power Supply Current
Test Condition
V0-VSS fOSC = 540KHz, VDD=5V Rf=33K
Min. 4.5 3.0 -
Typ. 0.45
Max. 5.5 7 0.75
Unit V V mA
VIH1
Input High Voltage (Except OSC1)
-
0.7VDD
-
VDD
V
VIL1
Input Low Voltage (Except OSC1)
-
-0.3
-
0.6
V
VIH2
Input High Voltage (OSC1)
-
VDD-1
-
VDD
V
VIL2
Input Low Voltage (OSC1)
-
-
-
1.0
V
VOH1
Output High Voltage (DB0 - DB7)
IOH = -0.1mA
0.8VDD
-
VDD
V
VOL1
Output Low Voltage (DB0 - DB7)
IOL = 0.1mA
-
-
0.4
V
VOH2
Output High Voltage (Except DB0 - DB7)
IOH = -0.04mA
0.8VDD
-
VDD
V
VOL2
Output Low Voltage (Except DB0 - DB7)
IOL = 0.04mA
-
-
0.1VDD
V A A
ILEAK IPUP
Input Leakage Current Pull Up MOS Current
VIN = 0V to VDD VDD = 5V
-1 75
80
1 85
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ST7920
AC Characteristics (TA = 25oC, VDD = 4.5V) Parallel Mode Interface
Symbol Characteristics Test Condition Internal Clock Operation fOSC OSC Frequency R = 33K External Clock Operation fEX External Frequency Duty Cycle TR,TF Rise/Fall Time 480 45 540 50 600 55 0.2 KHz % s 480 540 600 KHz Min. Typ. Max. Unit
Write Mode (Writing data from MPU to ST7920) TC TPW TR,TF TAS TAH TDSW TH Enable Cycle Time Enable Pulse Width Pin E Pin E 1200 140 10 20 40 20 25 ns ns ns ns ns ns ns
Enable Rise/Fall Time Pin E Address Setup Time Address Hold Time Data Setup Time Data Hold Time Pins: RS,RW,E Pins: RS,RW,E Pins: DB0 - DB7 Pins: DB0 - DB7
Read Mode (Reading Data from ST7920 to MPU) TC TPW TR,TF TAS TAH TDDR TH Enable Cycle Time Enable Pulse Width Pin E Pin E 1200 140 10 20 20 25 100 ns ns ns ns ns ns ns
Enable Rise/Fall Time Pin E Address Setup Time Address Hold Time Data Delay Time Data Hold Time Pins: RS,RW,E Pins: RS,RW,E Pins: DB0 - DB7 Pins: DB0 - DB7
Interface Mode with LCD Driver(ST7921) TCWH TCWL TCST TSU TDH TDM Clock Pulse with High Pins: CL1, CL2 Clock Pulse with Low Pins: CL1, CL2 Clock Setup Time Data Setup Time Data Hold Time M Delay Time Pins: CL1, CL2 Pin: D Pin: D Pin: M 800 800 500 300 300 -1000 1000 ns ns ns ns ns ns
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ST7920
AC Characteristics (TA = 25oC, VDD = 2.7V) Parallel Mode Interface
Symbol Characteristics Test Condition Internal Clock Operation fOSC OSC Frequency R = 18K External Clock Operation fEX External Frequency Duty Cycle TR,TF Rise/Fall Time 470 45 530 50 590 55 0.2 KHz % s 470 530 590 KHz Min. Typ. Max. Unit
Write Mode (Writing data from MPU to ST7920) TC TPW TR,TF TAS TAH TDSW TH Enable Cycle Time Enable Pulse Width Pin E Pin E 1800 160 10 20 40 20 25 ns ns ns ns ns ns ns
Enable Rise/Fall Time Pin E Address Setup Time Address Hold Time Data Setup Time Data Hold Time Pins: RS,RW,E Pins: RS,RW,E Pins: DB0 - DB7 Pins: DB0 - DB7
Read Mode (Reading Data from ST7920 to MPU) TC TPW TR,TF TAS TAH TDDR TH Enable Cycle Time Enable Pulse Width Pin E Pin E 1800 320 10 20 20 25 260 ns ns ns ns ns ns ns
Enable Rise/Fall Time Pin E Address Setup Time Address Hold Time Data Delay Time Data Hold Time Pins: RS,RW,E Pins: RS,RW,E Pins: DB0 - DB7 Pins: DB0 - DB7
Interface Mode with LCD Driver(ST7921) TCWH TCWL TCST TSU TDH TDM Clock Pulse with High Pins: CL1, CL2 Clock Pulse with Low Pins: CL1, CL2 Clock Setup Time Data Setup Time Data Hold Time M Delay Time Pins: CL1, CL2 Pin: D Pin: D Pin: M 800 800 500 300 300 -1000 1000 ns ns ns ns ns ns
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2001/10/18
ST7920
8-
ST7920 MPU
RS
VIH1 VIL1 TAS TAH
R/W
TPW TAH
E
TR TDSW TH
DB0-DB7
Valid data
TC
MPUST7920
RS
VIH1 VIL1 TAS TAH
R/W
TPW TR TAH
E
TDDR TH
DB0-DB7
Valid data
TC
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ST7920
AC Characteristics (TA = 25oC, VDD = 4.5V) Serial Mode Interface
Symbol Characteristics Test Condition Internal Clock Operation fOSC OSC Frequency R = 33K External Clock Operation fEX External Frequency Duty Cycle TR,TF TSCYC TSHW TSLW TSDS TSDH TCSS TCSH Rise/Fall Time Serial clock cycle Pin E 470 45 400 200 200 40 40 60 60 530 50 590 55 0.2 KHz % s ns ns ns ns ns ns ns 470 530 590 KHz Min. Typ. Max. Unit
SCLK high pulse width Pin E SCLK low pulse width Pin E SID data setup time SID data hold time CS setup time CS hold time Pins RW Pins RW Pins RS Pins RS
AC Characteristics (TA = 25oC, VDD = 2.7V) Serial Mode Interface
Symbol Characteristics Test Condition Internal Clock Operation fOSC OSC Frequency R = 18K External Clock Operation fEX External Frequency Duty Cycle TR,TF TSCYC TSHW TSLW TSDS TSDH TCSS TCSH Rise/Fall Time Serial clock cycle Pin E 470 45 600 300 300 40 40 60 60 530 50 590 55 0.2 KHz % s ns ns ns ns ns ns ns 470 530 590 KHz Min. Typ. Max. Unit
SCLK high pulse width Pin E SCLK low pulse width Pin E SID data setup time SID data hold time CS setup time CS hold time Pins RW Pins RW Pins RS Pins RS
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ST7920
ST7920 MPU
TCSS CS TSCYC SCLK Tf TSDS SID TSLW
TCSH
TSHW Tr TSDH
Valid data
C2.0c
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ST7920
/
Input PAD: E (No Pull-up)
Input PAD: RS, RW(with Pull-up)
Output PAD: CL1, CL2, M, D
Enable
DATA
I/O PAD: DB0 - DB7
C2.0c
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C
A B VCC R5 4.7K R4 4.7K R3 2.2K R2 4.7K R1 4.7K
D
C2.0c
R10 10K VCC JP1 HEADER 16 J1 1 2 3 CON3 R6 33K VCC 1 R7 2K C1 104 JK CON2 1
ST7920
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
2 1
VCC
JP2 HEADER 2
2 1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 R8 V0 V1 V2 VXA VXB VXC V3 V4 VSS VDD XRESET CL1 CL2 VDD M DOUT RS RW E VSS OSC1 OSC2 PSB D0 D1 D2 D3 D4 D5 D6 33 33 R9
LCD 32 COM x 160 SEG LCD VCC
JA CON2 2
2
2 1
VCC
C25 C26 C27 C28 C29 C30 C31 C32 192 191 190 189 188 187 186 185 C25 C26 C27 C28 C29 C30 C31 C32 C24 C23 C22 C21 C20 C19 C18 C17 96 95 94 93 92 91 90 89
C24 C23 C22 C21 C20 C19 C18 C17
3
3
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 S160 S159 S158 S157 S156 S155 S154 S153 S152 S151 S150 S149 S148 S147 S146 S145 S144 S143 S142 S141 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 S160 S159 S158 S157 S156 S155 S154 S153 S152 S151 S150 S149 S148 S147 S146 S145 S144 S143 S142 S141 S140 S139 S138 S137 S136 S135 S134 S133 S132 S131 S130 S129 S128 S127 S126 S125 S124 S123 S122 S121 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 S140 S139 S138 S137 S136 S135 S134 S133 S132 S131 S130 S129 S128 S127 S126 S125 S124 S123 S122 S121
S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 C33 C32 C31 C30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 D7 XOFF VOUT CAP3M CAP1P CAP1M CAP2P CAP2M VD2 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38
136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99
40/47
U1 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 ST7920 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 C32 C31 C30 4 VCC S65
S120 S119 S118 S117 S116 S115 S114 S113 S112 S111 S110 S109 S108 S107 S106 S105 S104 S103 S102 S101 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 S120 S119 S118 S117 S116 S115 S114 S113 S112 S111 S110 S109 S108 S107 S106 S105 S104 S103 S102 S101
S100 S99 S98 S97 S96 S95 S94 S93 S92 S91 S90 S89 S88 S87 S86 S85 S84 S83 S82 S81
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
S100 S99 S98 S97 S96 S95 S94 S93 S92 S91 S90 S89 S88 S87 S86 S85 S84 S83 S82 S81
4
S113
95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 S1 V0 V2 V3 VSS VDD CL1 SHL1 SHL2 CL2 DL1 DR1 DL2 DR2 M S49
S80 S79 S78 S77 S76 S75 S74 S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125
S80 S79 S78 S77 S76 S75 S74 S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61
S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41
5 Size Title B Number Date: File: 1-Mar-2001 D:\Buffer-2\7920V1.DDB
5
S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 C16 C15 C14 C13 C12 C11 C10 C9
S40 S41 S42 S43 S44 S45 S46 S47 S48 S96 S95 S94 S93 S92 S91 S90 S89 S88
124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97
S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 C16 C15 C14 C13 C12 C11 C10 C9
S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 C1 C2 C3 C4 C5 C6 C7 C8
28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 C1 C2 C3 C4 C5 C6 C7 C8
Sitronix ST7920 LCM
Revision
S114 S115 S116 S117 S118 S119 S120 S121 S122 S123 S124 S125 S126 S127 S128 S129 S130 S131 S132 S133 S134 S135 S136 S137 S138 S139 S140 S141 S142 S143 S144 S145 S146 S147 S148 S149 S150 S151 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 S79 S80 S81 S82 S83 S84 S85 S86 S87
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39
94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
S66 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 S79 S80 S81 S82 S83 S84 S85 S86 S87 S88 S89 S90 S91 S92 S93 S94 S95 S96 S97 S98 S99 S100 S101 S102 S103
Sheet 1 of 1 Drawn By: Paul Yung
6
6
U2
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
L1 WDG1603P
ST7921
1.2
A B
S104 S105 S106 S107 S108 S109 S110 S111 S112 S160 S159 S158 S157 S156 S155 S154 S153 S152 C D
2001/10/18
C
A B R5 4.7K R4 4.7K R3 2.2K R2 4.7K R1 4.7K
D
4.7u
LCD 32 COM x 160 SEG LCD VCC x 2
+
C2.0c
R10 10K VCC JP1 HEADER 16 J1 1 2 3 CON3 R6 33K VCC 1 R7 2K C1 104 JK CON2 1
ST7920
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
2 1
VCC
JP2 HEADER 2
2 1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 R8 V0 V1 V2 VXA VXB VXC V3 V4 VSS VDD XRESET CL1 CL2 VDD M DOUT RS RW E VSS OSC1 OSC2 PSB D0 D1 D2 D3 D4 D5 D6 33 33 R9
JA CON2 2
2
2 1
VCC
C25 C26 C27 C28 C29 C30 C31 C32 192 191 190 189 188 187 186 185 C25 C26 C27 C28 C29 C30 C31 C32 C24 C23 C22 C21 C20 C19 C18 C17 96 95 94 93 92 91 90 89
C24 C23 C22 C21 C20 C19 C18 C17
+ C3 4.7u C2
3
3
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 S160 S159 S158 S157 S156 S155 S154 S153 S152 S151 S150 S149 S148 S147 S146 S145 S144 S143 S142 S141 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 S160 S159 S158 S157 S156 S155 S154 S153 S152 S151 S150 S149 S148 S147 S146 S145 S144 S143 S142 S141 S140 S139 S138 S137 S136 S135 S134 S133 S132 S131 S130 S129 S128 S127 S126 S125 S124 S123 S122 S121 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 S140 S139 S138 S137 S136 S135 S134 S133 S132 S131 S130 S129 S128 S127 S126 S125 S124 S123 S122 S121
S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 C33 C32 C31 C30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 D7 XOFF VOUT CAP3M CAP1P CAP1M CAP2P CAP2M VD2 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38
136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99
41/47
U1 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 ST7920 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 C32 C31 C30 4 VCC S65
S120 S119 S118 S117 S116 S115 S114 S113 S112 S111 S110 S109 S108 S107 S106 S105 S104 S103 S102 S101 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 S120 S119 S118 S117 S116 S115 S114 S113 S112 S111 S110 S109 S108 S107 S106 S105 S104 S103 S102 S101
S100 S99 S98 S97 S96 S95 S94 S93 S92 S91 S90 S89 S88 S87 S86 S85 S84 S83 S82 S81
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
S100 S99 S98 S97 S96 S95 S94 S93 S92 S91 S90 S89 S88 S87 S86 S85 S84 S83 S82 S81
4
S113
95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 S1 V0 V2 V3 VSS VDD CL1 SHL1 SHL2 CL2 DL1 DR1 DL2 DR2 M S49
S80 S79 S78 S77 S76 S75 S74 S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125
S80 S79 S78 S77 S76 S75 S74 S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61
S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41
5 Size Title B Number Date: File:
5
S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 C16 C15 C14 C13 C12 C11 C10 C9
S40 S41 S42 S43 S44 S45 S46 S47 S48 S96 S95 S94 S93 S92 S91 S90 S89 S88
124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97
S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 C16 C15 C14 C13 C12 C11 C10 C9
S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 C1 C2 C3 C4 C5 C6 C7 C8
28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 C1 C2 C3 C4 C5 C6 C7 C8
Sitronix
Revision
S114 S115 S116 S117 S118 S119 S120 S121 S122 S123 S124 S125 S126 S127 S128 S129 S130 S131 S132 S133 S134 S135 S136 S137 S138 S139 S140 S141 S142 S143 S144 S145 S146 S147 S148 S149 S150 S151 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 S79 S80 S81 S82 S83 S84 S85 S86 S87
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39
94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
S66 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 S79 S80 S81 S82 S83 S84 S85 S86 S87 S88 S89 S90 S91 S92 S93 S94 S95 S96 S97 S98 S99 S100 S101 S102 S103
ST7920 LCM (Booster)
15-Aug-2001 Sheet 1 of 1 D:\adom\Documents\sch\7920_B~11.DDB Drawn By: Paul Yang
6
6
U2
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
L1 WDG1603P
ST7921
1.4
A B
S104 S105 S106 S107 S108 S109 S110 S111 S112 S160 S159 S158 S157 S156 S155 S154 S153 S152 C D
2001/10/18
Dot Matrix LCD Panel
Com 1-32
Seg 1-64 Dout
2Line 16Chinese Word (32 COM x 256 SEG)
DL1 VDD SHL1 SHL2 VSS V0
Seg 1-96
ST7921
V2 V3
DR2 DL2 DR1 CL1 CL2 M
DL1 VDD
Seg 1-96
SHL1 SHL2 VSS V0
ST7921
DR2 DL2 DR1 CL1 CL2 M
ST7920
DB0-DB7
VDD VSS CL2 CL1 M V0 V1 V2 V3 V4
Vcc(+5V/+3V) To MPU
VR
Regsister
Regsister
Regsister
Regsister
Regsister
VSS
ST7920
Note:Regsister=2.2K~10K ohm
VR=1K~30Kohm
LCD
C2.0c
42/47
V2
V3
2001/10/18
ST7920
ST7920 GB
A1A0 A1B0 A1C0 A1D0 A1E0 A1F0 A2A0 A2B0 A2C0 A2D0 A2E0 A2F0 A3A0 A3B0 A3C0 A3D0 A3E0 A3F0 A4A0 A4B0 A4C0 A4D0 A4E0 A4F0 A5A0 A5B0 A5C0 A5D0 A5E0 A5F0 A6A0 A6B0 A6C0 A6D0 A6E0 A6F0 A7A0 A7B0 A7C0 A7D0 A7E0 A7F0 A8A0 A8B0 A8C0 A8D0 A8E0 A8F0 A9A0 A9B0 A9C0 A9D0 A9E0 A9F0 B0A0 B0B0 B0C0 " " x * -- / ... ` ' B0D0 B0E0 B0F0 B1A0 B1B0 B1C0 B1D0 B1E0 B1F0 B2A0 B2B0 B2C0 B2D0 B2E0 B2F0 B3A0 B3B0 B3C0 B3D0 B3E0 B3F0 B4A0 B4B0 B4C0 B4D0 B4E0 B4F0 B5A0 B5B0 B5C0 B5D0 B5E0 B5F0 B6A0 B6B0 B6C0 B6D0 B6E0 B6F0 B7A0 B7B0 B7C0 B7D0 B7E0 B7F0 B8A0 B8B0 B8C0 B8D0 B8E0 B8F0 B9A0 B9B0 B9C0 B9D0 B9E0 B9F0 BAA0 BAB0

a o
a e e i i o u u u e

C2.0c
43/47
2001/10/18
ST7920
BAC0 BAD0 BAE0 BAF0 BBA0 BBB0 BBC0 BBD0 BBE0 BBF0 BCA0 BCB0 BCC0 BCD0 BCE0 BCF0 BDA0 BDB0 BDC0 BDD0 BDE0 BDF0 BEA0 BEB0 BEC0 BED0 BEE0 BEF0 BFA0 BFB0 BFC0 BFD0 BFE0 BFF0 C0A0 C0B0 C0C0 C0D0 C0E0 C0F0 C1A0 C1B0 C1C0 C1D0 C1E0 C1F0 C2A0 C2B0 C2C0 C2D0 C2E0 C2F0 C3A0 C3B0 C3C0 C3D0 C3E0 C3F0 C4A0 C4B0 C4C0 C4D0 C4E0 C4F0 C5A0 C5B0 C5C0 C5D0 C5E0 C5F0 C6A0 C6B0 C6C0 C6D0 C6E0 C6F0 C7A0 C7B0 C7C0 C7D0 C7E0 C7F0 C8A0 C8B0 C8C0 C8D0 C8E0 C8F0 C9A0 C9B0 C9C0 C9D0 C9E0 C9F0 CAA0 CAB0 CAC0 CAD0 CAE0 CAF0 CBA0 CBB0 CBC0 CBD0 CBE0 CBF0 CCA0 CCB0 CCC0 CCD0 CCE0 CCF0 CDA0 CDB0 CDC0 CDD0 CDE0 CDF0
C2.0c
44/47
2001/10/18
ST7920
CEA0 CEB0 CEC0 CED0 CEE0 CEF0 CFA0 CFB0 CFC0 CFD0 CFE0 CFF0 D0A0 D0B0 D0C0 D0D0 D0E0 D0F0 D1A0 D1B0 D1C0 D1D0 D1E0 D1F0 D2A0 D2B0 D2C0 D2D0 D2E0 D2F0 D3A0 D3B0 D3C0 D3D0 D3E0 D3F0 D4A0 D4B0 D4C0 D4D0 D4E0 D4F0 D5A0 D5B0 D5C0 D5D0 D5E0 D5F0 D6A0 D6B0 D6C0 D6D0 D6E0 D6F0 D7A0 D7B0 D7C0 D7D0 D7E0 D7F0 D8A0 D8B0 D8C0 D8D0 D8E0 D8F0 D9A0 D9B0 D9C0 D9D0 D9E0 D9F0 DAA0 DAB0 DAC0 DAD0 DAE0 DAF0 DBA0 DBB0 DBC0 DBD0 DBE0 DBF0 DCA0 DCB0 DCC0 DCD0 DCE0 DCF0 DDA0 DDB0 DDC0 DDD0 DDE0 DDF0 DEA0 DEB0 DEC0 DED0 DEE0 DEF0 DFA0 DFB0 DFC0 DFD0 DFE0 DFF0 E0A0 E0B0 E0C0 E0D0 E0E0 E0F0 E1A0 E1B0 E1C0 E1D0
C2.0c
45/47
2001/10/18
ST7920
E1E0 E1F0 E2A0 E2B0 E2C0 E2D0 E2E0 E2F0 E3A0 E3B0 E3C0 E3D0 E3E0 E3F0 E4A0 E4B0 E4C0 E4D0 E4E0 E4F0 E5A0 E5B0 E5C0 E5D0 E5E0 E5F0 E6A0 E6B0 E6C0 E6D0 E6E0 E6F0 E7A0 E7B0 E7C0 E7D0 E7E0 E7F0 E8A0 E8B0 E8C0 E8D0 E8E0 E8F0 E9A0 E9B0 E9C0 E9D0 E9E0 E9F0 EAA0 EAB0 EAC0 EAD0 EAE0 EAF0 EBA0 EBB0 EBC0 EBD0 EBE0 EBF0 ECA0 ECB0 ECC0 ECD0 ECE0 ECF0 EDA0 EDB0 EDC0 EDD0 EDE0 EDF0 EEA0 EEB0 EEC0 EED0 EEE0 EEF0 EFA0 EFB0 EFC0 EFD0 EFE0 EFF0 F0A0 F0B0 F0C0 F0D0 F0E0 F0F0 F1A0 F1B0 F1C0 F1D0 F1E0 F1F0 F2A0 F2B0 F2C0 F2D0 F2E0 F2F0 F3A0 F3B0 F3C0 F3D0 F3E0 F3F0 F4A0 F4B0 F4C0 F4D0 F4E0 F4F0 F5A0 F5B0
C2.0c
46/47
2001/10/18
ST7920
F5C0 F5D0 F5E0 F5F0 F6A0 F6B0 F6C0 F6D0 F6E0 F6F0 F7A0 F7B0 F7C0 F7D0 F7E0 F7F0
C2.0c
47/47
2001/10/18

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